ASIC DFT Architect / Technical Lead

Company Description SARACA is a global engineering R&D services company supporting 25+ Fortune 500 customers across MedTech, Aerospace, Rail, Automotive, Semiconductor, Defense, and Farm industries. The organization is ISO 13485 certified and has deep expertise in medical device design and development, including embedded software, UI/UX, mechanical engineering, systems, and product testing. SARACA offers specialized knowledge in IEC 62304, EU MDR, clinical and performance evaluation reports, and scientific writing for MedTech. With a team of 400+ engineers and management consultants, SARACA delivers solutions to complex business problems through onsite and offsite engagements worldwide. As an equal-opportunity employer, SARACA fosters a culture of innovation and learning, focused on helping customers grow faster and lead in their respective industries.

Job Title: ASIC Engineering Technical Leader – DFT

Location: San Jose, CA – Onsite

Start Date: Immediate Availability

Background Check: Mandatory

Role OverviewWe are seeking a highly motivated and technically strong ASIC Engineering Technical Leader with deep expertise in Design-for-Test (DFT). This role will focus on leading DFT development and implementation for next-generation ASICs supporting multi-100G to 1.6T coherent optical communication products.

The ideal candidate will have strong hands-on experience with scan insertion, SSN, ATPG, MBIST/LBIST, DFT integration, silicon debug, and Siemens Tessent tools, along with the ability to drive DFT execution from RTL through tapeout and post-silicon validation.

Key ResponsibilitiesLead implementation of SSN-based DFT architectures, including scan insertion, compression/decompression logic, MBIST, and LBIST.Use Siemens Tessent tools for RTL and gate-level netlist DFT implementation.Generate and deliver ATPG patterns for stuck-at, transition, cell-aware, and path-delay fault models.Develop and drive scan-based diagnosis methodologies for silicon failure analysis and debug.Provide post-silicon testing, validation, and failure-debug support.Evaluate design readiness for scan insertion through RTL and physical-design Scan DRC.Integrate and verify DFT fabrics and DFT IP within ASIC subsystems.Perform simulation and debug of non-timing and SDF back-annotated gate-level simulations.Develop test scripts and automate DFT processes using Python, Tcl, C++, or similar scripting/programming languages.Collaborate with RTL, physical design, verification, product engineering, and test/ATE teams.Drive DFT execution and technical decisions from architecture/concept through tapeout and silicon validation.Required QualificationsBachelor’s degree + 8 years of related experience, or Master’s + 6 years, or PhD + 3 years.Strong prior experience working with ASICs.Hands-on experience with scan insertion, DFT setup, integration, and validation.Experience implementing DFT architectures involving:Scan insertionCompression/decompressionMemory BIST (MBIST)Logic BIST (LBIST)Strong understanding of ASIC DFT flows and methodologies.Preferred Qualifications10+ years of ASIC engineering experience.10+ years of scan insertion and DFT setup/integration/validation experience.3+ years of SSN experience.Experience driving ASIC DFT activities from concept through tapeout.Experience working with ATE testers and semiconductor test teams.Strong RTL understanding and ability to debug DFT-related issues.Experience troubleshooting complex design issues, including clock-domain crossings (CDC).Familiarity with advanced semiconductor process/technology nodes and designs targeting high-speed and low-power applications.Strong hands-on experience implementing or integrating design blocks using Verilog/SystemVerilog.Experience with Siemens Tessent or comparable industry-standard DFT tools.Strong scripting/automation skills using Python, Tcl, or C++.