The role covers the full Neoverse Compute Subsystem scope: core configuration, CMN topology and parameterization, cache/SLC architecture, and CHI coherency behavior. The role also provides architectural guidance on chiplet and 3D-IC partitioning trade-offs, collaborating with dedicated packaging and interconnect teams on interface definitions. Responsibilities * Architect compute subsystems (CPU cluster, L2/L3/SLC cache, coherent mesh fabric) for next-generation ASIC and advanced Arm computing platform products. * Drive technology readiness: track Arm Neoverse CSS/CMN roadmap, identify IP gaps, and lead technical engagement with Arm on architecture and multi-die scope. Skills and Qualifications* Deep expertise in Arm CMN-series coherent mesh networks: topology sizing,HN/SN/RN placement, SLC optimization, QoS.
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