Company Description Known for its innovative small geometry solutions, our expertise encompasses data converter IP cores ranging from 6-bit to 14-bit resolutions and sampling rates up to over 20 Gsps. Apart from the above we need 10+ year DSP engineers with Serdes background. Education: B.E./M.Tech in Electrical/Electronics Engineering (Signal processing specialization).Experience: 10+ years in DSP algorithm development for SerDes PHYs.Tools & Languages:MATLAB, Python (algorithm modeling, post-processing).Cadence digital RTL tools .FPGA toolchains.Soft Skills: Analytical problem-solving, cross-functional collaboration, clear technical communication.Responsibilities Develop and optimize DSP algorithms for SerDes PHYs (Ethernet/PCIe/UCIe).Prototype DSP blocks on FPGA platforms for pre-silicon validation.Perform lab debug and silicon characterization of high-speed links.Collaborate with analog/mixed-signal teams on CDR, PLL/DLL, equalization schemes.Document workflows and support IP integration into customer SoCs.
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