Packaging Architect

Job Description MediaTek is seeking a talented and experienced technical leader with expertise in Packaging Architect, specifically 2.5D/3D/3.5D and STCO. The candidate should demonstrate ownership, high standards, strategic thinking, and customer obsession. Identify the optimal package architecture by balancing electrical, thermal, and mechanical performance, meeting project’s timeline.Working closely with internal and external partners on silicon-disaggregation and other chiplet strategies for advanced packages, including emerging-memory chiplet integrationPerform a trade-off analysis across silicon layout, die-to-die connectivity options, and package design/technology, evaluating their impact on key product metrics, including performance, cost, manufacturability, power efficiency, and form factor.Identifying critical elements for packaging roadmap, Partner with supply chain engineering experts to define packaging technology and material requirements for substrate fabrication, assembly, and raw material vendors.Stay informed about emerging packaging architectures by engaging with the product team and customers in the data center and high-end compute segments.Continuously monitor the competitive landscape in packaging technologies and solutions. Extensive hands-on experience (8+ years) in advanced semiconductor package architecture, including 2.5D/3D/3.5D, CoWoS-S/R/L, EMIB/EMIB-T, SoIC, HBM, FCBGA, HBPOP, and related technologies.Extensive experience in characterization and design of 2D, 2.5D, & 3D flip-chip & wafer-scale packaging solutions; experience in the areas of power-signal integrity, thermal-mechanical & system engineering domains.Proven track record of bringing up successful packages/ products with high power and high bandwidth applications from inception to product introduction.Extensive experience with high-speed interfaces, including SERDES, PCIe, die-to-die (D2D) interconnects and CPO & CPC, with a strong understanding of their impact on packaging technology choices, such as substrate selection, interconnect architecture, signal integrity, CPO & CPC integration, and thermal considerations.Experience in HBM on package integration, DDR integration, and working knowledge of various memory types.Experience in various EDA & CAD tools.Excellent communication skills.About 10-15% international travel required.

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