PMIC Architect

You're building the silicon infrastructure that powers AI. This is the bet. You will work directly with the Head of Engineering, digital architecture leads, and analog design team, and engage foundry partners and key customers at the architecture level. Define the multi-generation architecture roadmap — establish a clear migration path from initial process node to advanced nodes with improved power density and packaging integration 15+ years in power IC architecture; 5+ years at Principal level or higher in a fabless, IDM, or PMIC-focused semiconductor environment Deep expertise in multi-phase synchronous buck converter design — topology selection, loop compensation, stability analysis, and efficiency optimization across load Mixed-signal IC design fluency: gate driver design, current sensing techniques, analog control loops, and ADC/DAC integration in CMOS processes Hands-on experience with integrated passive components — on-chip or in-package inductors, capacitors, and their interaction with converter performance Advanced packaging familiarity: flip-chip, 2.5D/3D integration, bump map design, and thermal/electrical co-design for power-dense applications Experience driving power IC tape-outs from architecture definition through silicon bring-up and characterization Proficiency in power converter simulation: SPICE-level transient analysis, AC loop stability, and PVT corner sweeps

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