Senior RTL Design Architect - DRAM IP & Low-Power

Micron Technology in Boise, Idaho, is looking for a Principal RTL Design Engineer. You will lead the development of high-quality DRAM digital and mixed-signal IP, managing the full RTL design lifecycle to achieve power, performance, and area targets. Candidates should have strong experience in pre-silicon RTL design, ASIC low-power design methodologies, and proficiency in Verilog/SystemVerilog. Micron offers a robust benefits program and promotes a diverse and inclusive workplace.#J-18808-Ljbffr

Skills:
ASIC Design, Architectural Design, Candidate Sourcing, Compensation and Benefits, DRAM, IP (Internet Protocol), Intellectual Property (IP), Low Power, RTL Design, SystemVerilog, Technical/Engineering Design, Verilog Hardware Description Language

About the Company:
Micron Technology