SR. Principal ASIC Architect / Leader

Astera Labs is scaling the connectivity fabric behind the world's largest AI systems, and we are looking for a Distinguished Engineer to lead architecture for our next generation of high-speed connectivity silicon. You will define system- and chip-level architecture across PCIe, high-speed networking, and Ethernet-based subsystems that power hyperscale AI infrastructure, working at the intersection of silicon, system, and protocol design.

This is a foundational technical leadership role on a hyper-growth team enabling rack-scale AI. You will shape architectural direction for products that hyperscalers depend on for scale-up and scale-out connectivity, own critical tradeoffs across performance, power, latency, area, and cost, and partner deeply with customers and cross-functional teams to translate emerging use cases into industry-leading products

Key Responsibilities

Architecture LeadershipDefine and drive system- and chip-level architecture for high-speed connectivity products spanning PCIe (Gen 6/Gen 7), UALink, UCIe, and EthernetOwn micro-architecture specifications and ensure alignment across silicon, system, and software teamsContribute to standards-based and custom protocol development for next-generation AI infrastructureSystem Design & Tradeoff AnalysisTranslate hyperscale system requirements into scalable, efficient hardware architecturesDrive tradeoff analysis across performance, power, latency, area, and costArchitect high-speed, low-latency data paths and evaluate integration challenges at the SoC levelCross-Functional ExecutionPartner with RTL, Physical Design, Firmware, Validation, and Product Engineering to move architecture from concept to siliconSupport performance modeling, simulation, and architectural validationEngage directly with hyperscale customers and ecosystem partners to understand emerging use cases and requirementsTechnical Influence & MentorshipSet technical direction and raise the architecture bar across the connectivity portfolioMentor senior engineers and grow architectural depth across the R&D organizationBasic Qualifications

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field15+ years of experience in semiconductor architecture, ASIC design, or system engineeringStrong expertise in PCIe architecture (Gen 4/5/6+) and its broader ecosystemDeep understanding of networking and Ethernet technologies (25G/50G/100G/400G and beyond)Proven experience architecting high-speed, low-latency data paths and SoC-level integrationTrack record of driving architecture across the full chip development lifecycle, with strong analytical, tradeoff, and cross-domain collaboration skillsPreferred Qualifications

MS or PhD in Electrical Engineering, Computer Engineering, or a related fieldExperience with UALink, NVLink, UCIe, or other advanced interconnect protocolsBackground in AI/ML infrastructure, data center systems, or hyperscaler environmentsExperience with SerDes-based systems, high-speed PHY integration, switching, or RDMA technologiesFamiliarity with performance modeling tools, architectural simulators, and power/performance optimization at the system level